Published Paper Details:

There is a vast usage of binary addition in digital circuits as it is the basic arithmetic operation and it became indispensable in most of the digital systems counting ALU, microprocessors and DSP. Adders are the fundamental building blocks in digital integrated circuit based designs. Ripple Carry Adder (RCA) gives the most solid design but takes more computation time. The time crucial applications employ Carry Look-ahead scheme (CLA) is used to derive fast results but they lead to increase in area. Carry Select Adder is a concession between RCA and CLA in terms of area and delay. This paper shows a great vision on the design analysis of carry select adder based on Multiplexer using Verilog. The delay (9.069ns), power (20.98mW) is minimized and total coverage is 100%. The proposed architecture of carry select adder is simulated and verified in ModelSim10.1e, synthesized in Xilinx ISE14.7 and power analyzed in Quartus II9.1.