Published Paper Details:

Static Random Access Memory (SRAM) plays a vital role in modern digital systems due to its fast data access and compatibility with high-performance processors. However, continuous CMOS technology scaling has increased leakage current and standby power consumption, limiting its suitability for low-power applications. This work proposes a SAPON-based 4T2M SRAM architecture that integrates four CMOS transistors with two memristors to improve energy efficiency while maintaining reliable memory functionality. The memristors provide non-volatile data storage, and the SAPON leakage reduction technique minimizes standby leakage current without affecting normal read and write operations. The proposed design is implemented and evaluated using the Cadence Virtuoso design environment with Spectre simulation. Simulation results demonstrate that the proposed SRAM cell reduces power consumption from 404 nW to 379 nW compared with a conventional 6T SRAM cell. Although the propagation delay increases from 10.06 ns to 15.13 ns, the architecture maintains correct functionality and offers improved energy efficiency, making it suitable for IoT devices, embedded systems, and other low-power VLSI applications