Published Paper Details:

Side channel attacks (SCA) attack the hardware implementation of cryptography, but not the algorithms themselves. The attacks involve monitoring physical parameters that are affected by secret key operations in the hardware implementation and using statistical correlation techniques to recover the keys. Cryptographic chips used in embedded systems, smart cards, hardware security modules (HSMs), and SoCs are especially susceptible due to their limited physical environment. This paper reviews the various hardware techniques for defending against SCAs on power and timing channels. Wave Dynamic Differential Logic (WDDL), hardware masking techniques based on Boolean secret sharing and Threshold Implementations, constant time architecture design, and clock randomization are among those studied. These methods are analyzed for their effectiveness, cost in terms of area and performance overhead, scalability, and residual leaks. A comparative analysis will show the pros and cons of each technique in terms of PPA. Future directions for research include composable defense strategies and leakage verification for SCA-resilient cryptographic hardware.