Published Paper Details:

This work mainly focuses on developing accelerating CNN inference using an FPGA-based custom hardware accelerator on the PYNQ Z2 platform. The target application is of the dataset by MNIST for handwritten digit classification. A pre-trained CNN model is implemented, with convolutional and max-pooling layers designed in Verilog for FPGA execution. The software inference is performed using jupyter notebook, a python integrated environment. The PYNQ Z2 board facilitated an efficient design flow by integrating hardware and software elements, allowing for real-time processing of input data. The custom accelerator is built to implement the major layers of the CNN which includes 5x5 convolution layers, max pooling layers and a fully connected layer. This work shows the growing relevance of FPGAs in the hardware acceleration field for Deep Learning. By exploring the ability and potentiality of the PYNQ-Z2 board, this work showcases the potential of FPGA based accelerators in addressing the computational challenges posed by the CNNs and paves the way for future advancements and development in Hardware-Software co-design.