Published Paper Details:

The growing need for faster and more energy-efficient digital systems has made it crucial to design effective Arithmetic Logic Units (ALUs). Traditional ALU designs often struggle with issues related to power use, circuit complexity, and delays, especially as device sizes keep shrinking. This work details the design and implementation of an optimized 8-bit ALU using standard digital logic methods suitable for VLSI applications. The new architecture can perform a wide variety of arithmetic and logical operations while focusing on simpler hardware, lower delays, and better energy efficiency. A streamlined control unit is included to allow for smooth operation switching with minimal extra work. Simulation results show that the new ALU provides stable performance with lower power needs and reduced gate use compared to standard designs. These features make the proposed ALU a strong option for low-power embedded systems, high-speed processors, and modern digital computing platforms.