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ISSN Approved Journal No: 2320-2882 | Impact factor: 7.97 | ESTD Year: 2013
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Published Paper Details:
Paper Title
Low Power Consumption of CMOS Full Adder using Complementary Pass Transistor Logic
Authors
Pranusha N M, Meghana M, Sowmya D S, Shwetha Y S, Mrs. Annapurna Channigavi
Keywords
Low Power, Delay, CPTL, Full Adder, Higher Efficiency.
Abstract
The growing technology demands high speed, less power and small area processors. The adder circuit for example the ALU in CPU must offer high speed and low power for each calculation. Full adder circuit can be built using various metal-oxide semiconductor transistors. In this paper the work consists of a CMOS and a CPTL based full adder circuits implemented using 45nm technology. To ensure a good quality, low power consuming and less heat dissipation CPTL logic is preferable over a CMOS logic. The use of 4 terminal transistors helps to reduce error and delay at lower voltage and enrich the performance. Mobility of electrons and mobility of holes are having same width to get less power delay product.
IJCRT's Publication Details
Unique Identification Number - IJCRT2511332
Paper ID - 296454
Page Number(s) - c556-c564
Pubished in - Volume 13 | Issue 11 | November 2025
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Publisher Name - IJCRT | www.ijcrt.org | ISSN : 2320-2882
E-ISSN Number - 2320-2882
Cite this article
Pranusha N M, Meghana M, Sowmya D S, Shwetha Y S, Mrs. Annapurna Channigavi, "Low Power Consumption of CMOS Full Adder using Complementary Pass Transistor Logic", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.13, Issue 11, pp.c556-c564, November 2025, Available at :http://www.ijcrt.org/papers/IJCRT2511332.pdf
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Volume 14 | Issue 3
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Submit Manuscript Online Impact Factor: 7.97 Review Results : Within 02-03 Days Paper Publication : Within 02-03 Days
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ISSN: 2320-2882 Impact Factor: 7.97 and ISSN APPROVED Journal Starting Year (ESTD) : 2013
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ISSN: 2320-2882 Impact Factor: 7.97 and ISSN APPROVED Journal Starting Year (ESTD) : 2013
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