Published Paper Details:

Design for Test (DFT) has become a critical component of modern System-on-Chip (SoC) design due to increasing chip complexity. Addressing the challenges of generating test patterns for large-scale devices requires efficient solutions, such as Hierarchical DFT. This approach enables core-level DFT insertion and pattern generation, which is mapped to the top level, enhancing core reusability and reducing development time for SoCs with numerous IPs. This work focuses on developing a Hierarchical DFT flow using core-wrapping methodologies. Key elements include implementing dedicated and shared wrapper chains, integrating test compression logic, and performing Automatic Test Pattern Generation (ATPG) on DFT-inserted netlists. Internal and external mode patterns are generated and stored in PATDB (pattern database) format, with fault data and core descriptions saved in .tcd (tessent core description) files for retargeting. At the SoC level, a top-level wrapper consolidates multiple core instantiations with minimal top-level logic, enabling test pattern generation in Standard Test Interface Language (STIL) format for verification and silicon production tests. Considering the inherent complexity of Hierarchical DFT flows, optimizing key metrics such as test coverage, runtime, test duration, design area, development effort, and verification workload is essential. Achieving the right balance across these factors ensures an efficient and scalable solution for modern SoC designs. This work systematically evaluates different configurations and strategies to identify the most effective hierarchical DFT implementation, addressing the unique challenges posed by increasing design complexity and scalability demands in contemporary semiconductor technologies.