Published Paper Details:

Hardware accelerators for deep neural networks (DNNs) play a pivotal role in enabling low-latency inference on power-constrained edge and wearable devices. However, sustained high-performance computation in such accelerators leads to increased energy consumption, reducing their suitability for real-time mobile deployments. This paper presents a novel design of a coarse-grained DVFS-aware hardware accelerator that integrates dynamic voltage and frequency scaling (DVFS) to improve energy efficiency without compromising correctness or data throughput. To reduce control complexity, the system replaces traditional ML-based DVFS predictors with a lightweight finite-state machine (FSM)-based DVFS mimic. The proposed architecture includes five core components--Global Buffer, Data Dispatcher, Processing Element (PE) Array, DVFS Mimic Controller, and Accelerator Controller--all implemented in synthesizable SystemVerilog. Simulation results confirm that the architecture dynamically adapts computation delays based on simulated V/F levels while maintaining correctness in MAC and ReLU operations. The design is modular, scalable, and well- suited for future integration with AI workloads on edge SoCs.