Published Paper Details:

Arithmetic primitives play a critical role in performing computations on large numbers, particularly in arithmetic circuit implementations that involve operations like multiplication, addition, subtraction, and division. Given the significance of computations in central processing units (CPUs), optimizing the design of arithmetic circuits has been a key area of research for engineers. In the pursuit of developing energy- efficient, low-power portable processors for applications such as image processing, digital signal processing, and cryptography, it's essential to minimize factors like switching activity and cell count. This research focuses on the design of a reversible binary full adder circuit, a crucial component in evaluating the Energy Delay Product (EDP) for a variety of computing applications. The study introduces a novel reversible binary full adder based on the concepts of switching activity and logic decomposition. The fundamental building blocks for reversible full adders--such as Feynman Gates, Toffoli Gates and New Gates--are designed first. Then, leveraging these components, a new reversible binary full adder is developed using the proposed method. The results show that the proposed reversible full adder outperforms existing designs in terms of dynamic power dissipation. Additionally, a formula-based evaluation is conducted on the implementation results to estimate the EDP, which reveals a 32.3% improvement in EDP compared to the previously proposed full adder design.