Published Paper Details:

In modern computing systems, Static Random-Access Memory (SRAM) is a crucial component used in cache memory and embedded applications. However, traditional 6T SRAM cells face challenges including increased power consumption, reduced stability, and susceptibility to noise--especially at lower supply voltages. To address these limitations, this project proposes the design and implementation of a Single-Ended 11-Transistor (11T) SRAM cell using 18nm FinFET technology. The cell introduces an additional NMOS transistor to improve read and write operations, while minimizing half-select disturbance and enhancing Static Noise Margins (SNM). The FinFET-based design enables better leakage control and reduced short-channel effects, making the SRAM cell highly suitable for low-power applications. A comprehensive simulation is carried out in Cadence Spectre, and performance is evaluated across key metrics such as Read/Write Delay, SNM, and power consumption. Comparative analysis with conventional 6T, 10T, SE10T, and ST10T SRAM cells reveals that the proposed 11T design offers superior performance in terms of energy efficiency, stability, and delay. The results confirm that the cell is robust for near-threshold voltage applications and scalable for future low-power VLSI designs.