Published Paper Details:

Universal Asynchronous Receiver Transmitter (UART) communication is widely used in embedded systems, FPGA-based designs, and serial communication interfaces due to its simplicity and efficiency [1]. This paper presents an optimized FPGA-based UART module implemented using Verilog, designed for low latency, high-speed data transmission, and robust error handling mechanisms [12]. Traditional UART designs suffer from synchronization issues, baud rate mismatches, and inefficient buffering, leading to data corruption and transmission delays [3], [7]. To address these challenges, we propose a novel UART architecture with FIFO buffering, parity-based error detection, and baud rate optimization techniques [11], [14]. The proposed system ensures high reliability in real-time data transmission, making it suitable for IoT, industrial automation, and wireless communication applications [4], [19]. Compared to conventional implementations, our FPGA-based design achieves a 35% improvement in data throughput and a 28% reduction in latency [6], [9]. We also integrate an adaptive baud rate controller that dynamically adjusts based on the system clock frequency, reducing clock mismatches [10], [16]. Experimental results demonstrate the effectiveness of the proposed approach, validated on an FPGA prototype with varying baud rates ranging from 9600 to 115200 bps [8], [18]. Performance analysis confirms that our design outperforms existing UART implementations in terms of efficiency, scalability, and power consumption [5], [15]. This research contributes significantly to high-performance FPGA-based communication protocols [2], [13].