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ISSN Approved Journal No: 2320-2882 | Impact factor: 7.97 | ESTD Year: 2013
Call For Paper - Volume 13 | Issue 11 | Month- November 2025
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Published Paper Details:
Paper Title
32-Bit RISC-V Processor Architecture Design Using Fpga
Authors
G.Srilekha, G.Teja, K.Anusha, G. Ganesh, M. Damodara Rao
Keywords
Instruction set architecture, RISC-V, Simulation, Synthesis, VHDL, FPGA, Vivado and Power reports.
Abstract
RISC-V is a widely used open-standard instruction set architecture (ISA) based on RISC principles. It is supported by popular software tools like GNU, LLVM, DevOps, QEMU, and Spike. RISC-V can be used in simple embedded systems as well as high-performance applications like neural networks. This paper describes the design and implementation of a 32-bit RISC-V (RV32I) processor using VHDL and Vivado 2024.1 version. The processor's performance is tested through simulation, synthesis, and power analysis. The results provide insights into execution speed and power consumption, proving that an FPGA-based RISC-V processor is a good choice for low-power and efficient computing.
IJCRT's Publication Details
Unique Identification Number - IJCRT2504433
Paper ID - 281958
Page Number(s) - d737-d746
Pubished in - Volume 13 | Issue 4 | April 2025
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Publisher Name - IJCRT | www.ijcrt.org | ISSN : 2320-2882
E-ISSN Number - 2320-2882
Cite this article
G.Srilekha, G.Teja, K.Anusha, G. Ganesh, M. Damodara Rao, "32-Bit RISC-V Processor Architecture Design Using Fpga", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.13, Issue 4, pp.d737-d746, April 2025, Available at :http://www.ijcrt.org/papers/IJCRT2504433.pdf
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Volume 13 | Issue 11
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Submit Manuscript Online Impact Factor: 7.97 Review Results : Within 02-03 Days Paper Publication : Within 02-03 Days
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ISSN: 2320-2882 Impact Factor: 7.97 and ISSN APPROVED Journal Starting Year (ESTD) : 2013
ISSN and 7.97 Impact Factor Details
ISSN: 2320-2882 Impact Factor: 7.97 and ISSN APPROVED Journal Starting Year (ESTD) : 2013
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