Published Paper Details:

In modern computing systems, achieving a balance between accuracy and power consumption is crucial. As technology gets smaller, it becomes harder for traditional methods to work efficiently. This is applicable even in tasks like videos, signal processing, where exact accuracy is not always needed. So, we go for approximate adders for applications in which accuracy is not significant but there is a need for reduced power consumption and delay. Approximate adders often skip some computations to achieve better performance in terms of energy efficiency and speed. The project focuses on the designing of exact mirror adder, two types of approximate adders single exact single approximate adder (SESA) and single exact dual approximate adder (SEDA) circuit using 18nm Fin FET technology. These circuits are evaluated using the Cadence virtuoso tool. SESA and SEDA have two modes of operation, exact mode for accuracy of the adder and approximate mode for low-power consumption. Using SESA and SEDA, modes can be shifted easily and also allow to vary the amount of approximation .To demonstrate the practical utility of the adders, applied SESA and SEDA architectures in two key application areas: image enhancement and checksum generation.