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  Published Paper Details:

  Paper Title

Redundant-Transition-Free Low Power TSPC Dual-Edge-Triggering Flip-Flop With Clocked Single Transistor

  Authors

  Dr.G.Jhansi,  Y.Subhashini

  Keywords

Flip-Flop, Dual-Edge Triggered, Low Power, TSPC (TrueSingle-PhaseClock), Redundant- Transition-Free Clocked Single Transistor

  Abstract


In the age of artificial intelligence (AI) and graphics processing units (GPUs), the flip-flop (FF) has emerged as one of the processor's most power- hungry elements. A unique single- phase-clock dual edge triggering (DET) FF employing a single transistor clocked (STC) buffer (STCB) is suggested as a solution to this problem. The clock redundant transitions (RTs) and internal RTs present in previous DET designs are eliminated entirely by the STCB's use of a single- clocked transistor in the data sampling path. The suggested STC-DET beats the previous state-of-the- artlow-powerDET in power consumption by 14% and 9.5%, at 0.4 and 0.8 V, respectively, when running at 10% switching activity, as shown by post-layout simulations in 22 nm fully depleted silicon on insulator (FD-SOI) CMOS. Among the DETs, it also attains the lowest power-delay-product (PDP).

  IJCRT's Publication Details

  Unique Identification Number - IJCRT2501035

  Paper ID - 275128

  Page Number(s) - a320-a324

  Pubished in - Volume 13 | Issue 1 | January 2025

  DOI (Digital Object Identifier) -   

  Publisher Name - IJCRT | www.ijcrt.org | ISSN : 2320-2882

  E-ISSN Number - 2320-2882

  Cite this article

  Dr.G.Jhansi,  Y.Subhashini,   "Redundant-Transition-Free Low Power TSPC Dual-Edge-Triggering Flip-Flop With Clocked Single Transistor", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.13, Issue 1, pp.a320-a324, January 2025, Available at :http://www.ijcrt.org/papers/IJCRT2501035.pdf

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ISSN: 2320-2882
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Journal Starting Year (ESTD) : 2013
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ISSN and 7.97 Impact Factor Details


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ISSN
ISSN: 2320-2882
Impact Factor: 7.97 and ISSN APPROVED
Journal Starting Year (ESTD) : 2013
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