Published Paper Details:

The recent usage of deep sub-micron tenure was due to the rise in demand for integration of much more components on to a single chip for better performance with less power consumption. ASIC consists of logic blocks which are pre-designed and pre-verified in system library functions which lead to the success for the rapid increase of integrated system. Standard cell methodology is a phenomenon of designing ASICs (Application Specific Integrated Circuits) that is used in designing semiconductors with digital-logic features [1]. The cells or logic gates selected to build the library depends on the design requirement. These cells when used in the Semi-Custom Design Flow have to meet certain functions and performance. A successful and efficient implementation of a Semi-Custom Design depends on the standard cells in the library. Therefore, it is important to have a high quality cell library [2]. Modern integrated circuits are very large containing over a billion of transistors. Designs based on sub-micron technologies will always be a challenging task for the manufacturer to produce it at a very competitive cost. One approach is to use 'Cell-Based' implementation using Standard cell library [3]. Standard cells allow tools to automatically synthesize a circuit and optimize area, power consumption and timing. The state of the art Standard Cell Library using CMOS technology In this paper, overview of survey on history and development of standard cell library by considering different specifications like area, power, speed and driving strength in different technology(90nm, 65nm, 45nm and so on) for different applications is discussed.