Published Paper Details:

The emerging growth of the Internet of Things has created various opportunities to develop high-value, prioritized solutions in digital systems. A prime factor in achieving timing synchronization in high-stability digital devices is the need for a robust technical system with a stabilized clock. In low-energy satellite synchronization sources, there is a problem with frequency tuning, where the main system cannot cope with the evening process. The primary issue in existing frameworks for synchronization in network-on-chip creation is considered a timing problem and evaluated as a dynamic network. The presented system focuses on creating a stabilized network-on-chip model, in which clock synchronization is achieved using a frequency-tuneable all-digital network-on-chip. The configurable network concept framework is developed with the help of a stabilized clock distribution network. The percentage system of the clock is designed to compensate for the physical connections in the network. To evaluate the proposed system's performance and quality of network synchronization, power analysis and latency calculations are conducted.