Published Paper Details:

Modern chip designs, driven by rapid VLSI advancements, have become complex and compact, making post-fabrication testability essential for ensuring operational compliance. Design-for-Testability (DFT) techniques are crucial for fault identification after manufacturing, significantly reducing the need for exhaustive functional tests on numerous devices. DFT enhances controllability and observability across design nodes, facilitating effective error detection without extensive individual device testing. Among various DFT methodologies, the hierarchical approach is recognized for its efficiency in verifying manufacturing correctness. This method uses Automatic Test Pattern Generation (ATPG) to create test vectors from a block's netlist, aiming for comprehensive fault coverage with minimal time investment. By integrating compression logic, the number of generated test vectors is significantly reduced. Validation occurs at the block level to ensure compatibility with top-level pins through logical simulation, confirming timing and layout integrity. For blocks with inadequate coverage, a coverage analysis is conducted, followed by test point insertion to enhance coverage targets. The paper concludes with insights into future trends in DFT that can be utilized to improve coverage factor and have a greater yield along with Test point Insertion integration in DFT designs.