Published Paper Details:

Fault detection systems in the pre-silicon stage have become increasingly important in ensuring the dependability of IC designs as the scale and complexity of VLSI designs continue to increase.Testing is very important for the diagnosis of faults at an earlier stage for any system, in particular, it is critical for the integrated circuits as the replacement is highly expensive. It is very complex to scaled-down the technologies due to the non-availability of mature models. In this thesis, various test and fault diagnosis techniques are studied, and modified algorithms for improvements are applied to chosen FinFET-based circuits. The effectiveness of the Built-in Self-Test (BIST) in finding faults is analysed concerning salient figures of merit including maximum fault coverage, speed, power dissipation, and test area overhead leading to improved design performance. A systolic array multiplier 94X4 is designed with reversible gates and Built-In Logic Block Observer (BILBO) logic is used for fault injection. Further, in this thesis suitability of PODEM algorithm for fault location is explored It is found that the application of AXI BIST results in significant improvement in speed (74%) and consumes power by 50%. Fault coverage (> 95%) is maximized through ROBDD. A reduced setup time could be achieved (2.3 ns) through selected Vedic algorithms.