Published Paper Details:

For Area-efficient VLSI architecture a Two-operand binary adder is designed where in which area is more and speed of operation is low, because of these limitations a new architecture with Three-operand binary adder logic is to be designed instead of previous architecture which performs 3-9 times faster than the previous architecture. Three-operand binary adder is the basic functional unit to perform the modular arithmetic and various Cryptography and Pseudorandom Bit Generator (PRBG) algorithm. Carry save adder (CS3A) is widely used technique to perform the Three-operand binary adder. However the ripple-carry stage in CS3A leads to a high propagation delay. Moreover a parallel prefix Two-operand binary adder such as Han-Carlson (HCA) can also be used for Three-operand addition that significantly reduces the critical path delay a cost of additional hardware. Three-operand binary addition significantly decreases area and power consumption. Hence a new High-speed and Area efficient adder architecture is proposed using pre-compute bitwise addition followed by carry prefix computation logic to perform the Three-operand binary addition. With this Logic a new architecture is to be designed, for 16-bit Three-operand binary addition which is called as 16-bit Three-operand binary adder. To design this logic we are using Xilinx ISE, ModelSim software with VHDL, Verilog languages.