Published Paper Details:

Basically, cryptographic algorithms consists of large integers like RSA and Diffie-hellman. This algorithm performs mostly time consuming operations like modular multiplication operation. The implementation of modular multiplication function takes more than 75 percent of time within in the RSA for more than 1024-bit moduli. Here fast multiplier architectures are used to minimize the delay and increase the throughput using parallelism and pipelining. But this architectures occupy large area and gives less efficiency. In this paper it consists of integration of fast Fourier transform method into the framework and as well as it produces improved FFT-based Montgomery modular multiplication (MMM) algorithm to obtain high area-time efficiency. In existed system zero padding operation is performed to compute the modular multiplication steps directly using cyclic and nega cyclic convolutions. Now to reduce the convolution length by half in the number weighted theoretic algorithm, FFT algorithm is used which provide fast convolution computation. In proposed algorithm a general method is introduced for efficient parameter selection. In this proposed architecture single and double butterfly structures are designed to get low area-latency solutions and these are implemented on Xilinx Virtex-6 FPGAs. So from this it can be observed that the proposed system gives better area-latency efficiency compared to the existed system.