Published Paper Details:

Design of vedic multiplier based on fault coverage is proposed. The multiplier is design for 64 bit. The multiplier is design using Urdhava Tiryakbhyam method. In these proposed design fault detection is proposed. The circuit behaviour is check by designing build in self test circuit. The circuit covers all 64 bit fault coverage, which means the circuit shows the status of a multiplier whether it provides correct or incorrect output. The circuit is tested on various input combinations. Those combinations are provided by LFSR. The proposed Vedic multiplier design is tested. The circuit is ready very efficient which can be tested for various multiplier. The ALU is the heart of any processor or the any complex system. To increase the speed of any system, it is required to increase the speed of ALU, but with low power consumption and for that portable life is required .Vedic multiplier gives faster processing speed in terms of array multiplier. VLSI designing techniques are the source to reengineering any digital electronics circuitry. In this paper a low power 64 bit ALU is designed in VHDL.