Published Paper Details:

This work explores the new low power approaches for VLSI logic. While designing a VLSI system power dissipation is one of the major concerns. Up to a certain time dynamic power was the single largest concern; however as the technology feature size shrinks static power has become an important issue as dynamic power. A well-known previous technique called the sleep transistor technique cuts off Vdd and/or Gnd connections of transistors to save leakage power consumption. However, when transistors are allowed to float, a system may have to wait a long time to reliably restore lost state and thus may experience seriously degraded performance. Therefore, retaining state is crucial for a system that requires fast response even while in an inactive state. The two common approaches are sleepy stack and sleepy keeper. Both methods are excellent in this regard. The static and dynamic power of sleepy stack is considerably low. But it has a delay penalty and its area requirement is maximum compared with other processes. Again the sleepy keeper process possesses excellent speed criteria but it requires more static and dynamic power than sleepy stack. Our goal is to trade off between these limitations and thus propose new methods which reduce both leakage and dynamic power with minimum possible area and delay trade off.