Published Paper Details:

The main aim of the paper is simulation and synthesis of the 16-bit RISC CPU based on MIPS. The project involves design of simple RISC processor and simulating it. A Reduced Instruction Set Compiler (RISC) is a microprocessor that has been designed to perform a small set of instructions, with the aim of increasing the overall speed of the processor .In this work, we analyze MIPS instruction format, instruction data path, decoder module function and design theory based on RISC (Reduced Instruction Set Computer) CPU instruction set. We use pipeline design process to simulate successfully, which involves instruction fetch (IF), instruction decoder (ID), execution (EXE), data memory (MEM), write back (WB) modules of 16-bit CPU based on RISC CPU instruction set. In this project we are using hazard detection unit helps for accurate behavior of the system. In this project for simulation we use Modelsim for logical verification, and further synthesizing it on Xilinx-ISE tool using target technology and performing placing & routing operation for system verification. The language we used here is VERILOG, and tools required here are XILINX -ISE 13.1-Synthesis.This processor make it especially suited to embedded control applications.