Published Paper Details:

Abstract : The necessity of high speed clock can be fulfilled in two ways, either a very high frequency clock is directly used or low frequency clock is passed through a clock multiplier to have a high frequency clock. The first method is becomes inadequate when the required speed becomes very high (few gigahertz). The second method might be an alternative for the similar purpose. CMU is used to generate high frequency clock. The DLL based CMU is generally used in the industry to get higher speed clock. At high speed, some of the issues come into the picture strongly to achieve high quality performance. The main constraints appear due to limitations of different building blocks of the DLL. Each different unit has different limitations that affect the overall performances. Phase and frequency detector (PFD) imposes the problem of its resolution. The PFD resolution should be high in order to minimize static phase error that helps in reduction of jitter. It reduction in static phase error increases the closed loop speed. The current mismatch in charge pump is greatly affected due to low resolution of the PFD. Hence we find, high resolution is a stringent requirement to achieve high speed in DLL. Generally PFD is realized by conventional method (D flip flop based) but this project used pre-charge type PFD which offers higher resolution. Actually, PFD is closed loop system so the delay of the circuit becomes an important parameter to determine the speed of the same.