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  Published Paper Details:

  Paper Title

DESIGN AND ANALYSIS OF VEDIC MULTIPLIER USING FULL SWING MODIFIED GATE DEFUSED INPUT METHOD

  Authors

  Bavusaheb. B.Kunchanur,  P.Usha

  Keywords

low power, GDI, modified GDI, hybrid full adder, mentor graphics, PDP, Vedic multipliers

  Abstract


The complexity in VLSI design increases with an increase in the level of integration. Due to the portable electronics area, power and delay have become the most important factors. In conventional CMOS design, the area, power and delay are more compared to other Low power techniques. In this paper Vedic multiplier is designed using different low power techniques, such as, conventional CMOS, GDI, Modified GDI, full swing defused gate style and hybrid structure which has a combination of GDI, TG, XOR, XNOR and pass transistor logic. All the designs are compared for area, power and delay. The power delay product graph is drawn for all the designs. The design and simulation are done in MENTOR GRAPHICS TOOL in 45 nm technology.

  IJCRT's Publication Details

  Unique Identification Number - IJCRTNCES047

  Paper ID - 180495

  Page Number(s) - 301-306

  Pubished in - Volume 6 | Issue 1 | December - 2017

  DOI (Digital Object Identifier) -   

  Publisher Name - IJCRT | www.ijcrt.org | ISSN : 2320-2882

  E-ISSN Number - 2320-2882

  Cite this article

  Bavusaheb. B.Kunchanur,  P.Usha,   "DESIGN AND ANALYSIS OF VEDIC MULTIPLIER USING FULL SWING MODIFIED GATE DEFUSED INPUT METHOD", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.6, Issue 1, pp.301-306, December - 2017, Available at :http://www.ijcrt.org/papers/IJCRTNCES047.pdf

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ISSN: 2320-2882
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ISSN: 2320-2882
Impact Factor: 7.97 and ISSN APPROVED
Journal Starting Year (ESTD) : 2013
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