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INTERNATIONAL JOURNAL OF CREATIVE RESEARCH THOUGHTS - IJCRT (IJCRT.ORG)
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ISSN Approved Journal No: 2320-2882 | Impact factor: 7.97 | ESTD Year: 2013
Call For Paper - Volume 12 | Issue 7 | Month- July 2024
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Paper Title
THE DESIGN AND VERIFICATION OF A 32-BIT RISC V PROCESSOR USING VEDIC MATHEMATICS
Authors
Girish H, Vajjala Sai Sree Hari, Ponde Lakshmi Narasimha, P N Shreya, Dadigala Bhargavi
Keywords
Reduced Instruction Set Computer, Von Neumann architecture, Verilog HDL, Vedic Mathematics, Urdhva-Tiryagbhyam Sutra.
Abstract
Vedic multiplier architecture is used in the construction of a 32-bit RISC V processor to improve speed and decrease computational complexity. Its Vedic Sutra-based ALU and MAC units, which are implemented in Verilog HDL and simulated using the Xilinx design suite, lower power consumption and latency as compared to traditional architectures. Comprising of conventional components such as Control Unit, Register Bank, Programme Counter and Memory. The processor can carry out up to 16 instructions. It is an effective option for a variety of computer jobs since it provides increased speed, decreased power consumption, and reduced area utilisation.
IJCRT's Publication Details
Unique Identification Number - IJCRTAB02172
Paper ID - 260013
Page Number(s) - 1130-1135
Pubished in - Volume 12 | Issue 5 | May 2024
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Publisher Name - IJCRT | www.ijcrt.org | ISSN : 2320-2882
E-ISSN Number - 2320-2882
Cite this article
Girish H, Vajjala Sai Sree Hari, Ponde Lakshmi Narasimha, P N Shreya, Dadigala Bhargavi, "THE DESIGN AND VERIFICATION OF A 32-BIT RISC V PROCESSOR USING VEDIC MATHEMATICS", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.12, Issue 5, pp.1130-1135, May 2024, Available at :http://www.ijcrt.org/papers/IJCRTAB02172.pdf
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ISSN: 2320-2882 Impact Factor: 7.97 and ISSN APPROVED Journal Starting Year (ESTD) : 2013
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ISSN: 2320-2882 Impact Factor: 7.97 and ISSN APPROVED Journal Starting Year (ESTD) : 2013
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