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  Published Paper Details:

  Paper Title

SRAM Cell Design Using FinFET for Low Power and Delay

  Authors

  Veerappa S C,  S K Fazle Umar,  Sai Dhanush R N,  Syed Avaiz,  Vishwa Periaswamy

  Keywords

SRAM Cell Design Using FinFET for Low Power and Delay

  Abstract


This paper introduces an approach utilizing a fin-shaped field-effect transistor to illustrate the structure of a 6T SRAM cell. The primary goal is to enhance the presentation's competitive edge while concurrently reducing the power usage and read/write delay inherent in conventional 6T SRAM cell designs. Given the increasing demand for rapid mobile computing, traditional CMOS SRAM cell configurations face performance constraints and significant power demands. This research undertakes a thorough examination of power consumption and read/write delay parameters associated with low-power SRAM cell designs. Furthermore, an exhaustive comparative analysis is performed between 45nm nano-scaled technologies and the emerging FinFET-based 6T SRAM cells, with a particular emphasis on their respective power efficiency and operational speed characteristics.

  IJCRT's Publication Details

  Unique Identification Number - IJCRTAB02149

  Paper ID - 259985

  Page Number(s) - 984-991

  Pubished in - Volume 12 | Issue 5 | May 2024

  DOI (Digital Object Identifier) -   

  Publisher Name - IJCRT | www.ijcrt.org | ISSN : 2320-2882

  E-ISSN Number - 2320-2882

  Cite this article

  Veerappa S C,  S K Fazle Umar,  Sai Dhanush R N,  Syed Avaiz,  Vishwa Periaswamy,   "SRAM Cell Design Using FinFET for Low Power and Delay", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.12, Issue 5, pp.984-991, May 2024, Available at :http://www.ijcrt.org/papers/IJCRTAB02149.pdf

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ISSN: 2320-2882
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Journal Starting Year (ESTD) : 2013
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ISSN and 7.97 Impact Factor Details


ISSN
ISSN
ISSN: 2320-2882
Impact Factor: 7.97 and ISSN APPROVED
Journal Starting Year (ESTD) : 2013
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