Published Paper Details:

The rapid adoption of multi-level inverters in electric drives and renewable energy systems underscores their pivotal role in modern power electronics. These inverters offer significant advantages over traditional two-level inverters, including reduced dv/dt stress, lower total harmonic distortion (THD), and diminished common mode current. However, prevalent multi-level inverter topologies, such as neutral point clamped, cascaded H-bridge, and flying capacitor inverters, present challenges that impede optimal performance. This paper introduces a novel three-phase two-level inverter topology aimed at addressing common mode voltage and current issues inherent in existing designs. The proposed topology integrates two cascaded converters and leverages device junction capacitance (DJC) to implement a neutral point clamping methodology, thereby enhancing the inverter's operational stability and efficiency. A comprehensive analysis using the switching function concept reveals the impact of DJC on the inverter's performance. The study further explores a sophisticated PWM control scheme designed to optimize the modulation process and minimize common mode voltage variations. Simulation results, conducted using MATLAB, demonstrate the superiority of the proposed topology over conventional and H7 two-level inverters. Key performance metrics such as pole voltage, phase voltage, common mode voltage, and total harmonic distortion (THD) are evaluated, showcasing significant improvements. The proposed inverter achieves a THD reduction to 61.41%, compared to 91.81% and 88.01% for conventional and H7 inverters, respectively. This research not only advances the field of power electronics but also provides practical insights for engineers and researchers. By addressing critical issues in multi-level inverter design, the proposed topology paves the way for more efficient and reliable power conversion systems, contributing to enhanced energy efficiency and sustainability in contemporary applications.