Published Paper Details:

The emergence of memristor-based digital logic gates presents a promising alternative to conventional IC design paradigms, signaling a new era in computing architecture. Leveraging memristors for logic gate design offers simplicity in manufacturing, as memristors can be integrated atop the poly-silicon gate of NMOS transistors, facilitating increased transistor density on a chip. In this context, this work focuses on the development and analysis of a 3-bit encoder utilizing Memristor Ratioed Logic (MRL), aiming to harness its potential for low-power applications. The proposed encoder design showcases superior power efficiency compared to conventional CMOS designs, positioning it as a compelling solution for energy-conscious computing environments. By employing MRL, the encoder serves as a versatile platform for modeling various combinational logic circuits, demonstrating its efficacy in diverse computational tasks. The primary objective of this work is to design and analyze a 3-bit encoder employing various logical methodologies, utilizing LTspice for simulation and evaluation.