Published Paper Details:

With the increase in complexity of System-on-Chip (SoC) designs to enable greater logic integration driven by Moore's law and beyond Moore principles, the process of verification of the design becomes increasingly complex. To facilitate faster and more efficient verification, a standard methodology like the Universal Verification Methodology (UVM) is essential. UVM provides a library of SystemVerilog (SV) base classes, which can be extended to meet specific requirements. Verification is a crucial component in chip design and fabrication process, necessitating thorough testing at both the block and full-chip levels. This paper focuses on the block-level verification of an IP, General Purpose Input/Output (GPIO) Controller. Utilizing the UVM architecture, a constrained random testbench has been developed to create a reusable and robust verification environment. The testbench supports multiple tests to ensure comprehensive design coverage, aiming for 100% code coverage. Advanced SystemVerilog features, including assertions, coverpoints, covergroups, and multithreading, are integrated into the testbench to enhance its effectiveness.