Published Paper Details:

Numerous human-centric applications, including financial services, accounting, tax computation, and currency conversion, rely heavily on decimal computation. A large number of scholars are therefore interested in the development and use of radix-10 arithmetic units. Multiplication isn't only one of the most common but also one of the most complicated and power-hungry operations in fundamental decimal arithmetic. Consequently, this study delves into this matter and examines a generic design technique that minimizes power/energy consumption by localizing switching activity, all while maintaining goal performance. In the same way that Karatsuba's algorithm decomposes a digit multiplier into smaller ones, this approach also allows for varying sizes of the multiplicand and multiplier. Using symmetric and asymmetric divisions of varying sizes, we derive designs with unique properties. The suggested designs surpass prior options for decimal multiplication and provide intriguing area-delay numbers when tested with operands which have 16 digits long, in comparison to traditional binary multipliers. Verilog HDL will be used for its development. To carry out the simulation and synthesis, the Xilinx ISE tool is used.