Published Paper Details:

Identifying and correcting faults in IC design have become critical stages as the complexity of digital VLSI circuits continues to grow. Presented in this paper is a novel fault identification model based on deep learning (DL), utilizing a distinct type of artificial neural network (ANN) known as stacked sparse autoencoder (SSAE). The main goal of this proposed model is to tackle the challenge in the exploration domain by employing SSAE for identifying features and detecting anomalies in extensive electronic circuits. The model comprises three key stages: test pattern creation, feature reduction, and fault detection. Unsupervised learning using training data is implemented in the SSAE phase to enhance feature extraction. The evaluation of feature extraction effectiveness involves modifying the architecture of the SSAE network. The strategy achieves 99.3% fault coverage with ATALANTA and reduces features by 99.7% using SSAE for test patterns.