Published Paper Details:

As semiconductor technology advances, the escalating demand for efficient power consumption in electronic devices, especially mobile gadgets, has become paramount. In pursuit of low-power circuits, this study explores various techniques, including the proposed Advance Leakage Method, to mitigate power loss, emphasizing the critical issue of leakage power, which can contribute up to 50% of overall power consumption. The study examines the dissipation of power due to leakage in VLSI circuits. A comprehensive analysis of leakage reduction methods, such as the Stack Technique, LECTOR Technique, Source Biasing Approach, Stack ONOFIC Approach, and the Proposed Approach, is presented. The study employs CMOS inverter models, revealing a significant reduction in leakage power by 50%, demonstrating the efficacy of the proposed method. The results, including power consumption and propagation time for various circuits and techniques, are tabulated and discussed, providing valuable insights for future low-power VLSI circuit designs.