Published Paper Details:

Most applications, including e-commerce, online banking, the military, satellite and wireless communications, electronic devices and appliances, etc., consider data security to be a major factor and give it significant weight. By transforming the data into a format that is difficult for unneeded people to understand, cryptography is a technique used to keep data secure and private. This method offers a reliable, affordable means of protecting our data secrecy and aids in data integrity verification. The side channel attacks that cryptography is subject to make it difficult to provide error-free data. The proposed AES accelerator improves the horizontal (temporal) SCA hiding of asynchronous logic operations using a timing-boundary-free input arrival time randomizer and a skewed-delay controller while achieving vertical (amplitude) SCA hiding via an area-efficient dual-rail mapping approach and a ZV compensated substitution-box (S-Box). Additionally, a chaotic sequence is used in between each step of the cypher text generation process. As a result, the design will reduce the area overhead, offer strong defence against side channel attacks, and increase the system dependability. The proposed design is implemented in Xilinx Vivado 2018.3, and final result of the simulation are used to validate the output