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  Published Paper Details:

  Paper Title

DESIGN & IMPLEMENTATION OF LOW POWER & HIGH FAST SUBSCALAR MULTIPLIER

  Authors

  D. GEETHANJALI1,  P. YASODHA DEVI

  Keywords

lower power consumption, XILINX ISE Design, FFT processor and Fourier transform.

  Abstract


Propose a Sub Scalar Computations multiplier that is high speed yet energy efficient. The approach is to round the operands to the nearest exponent of two. This way the computational intensive part of the multiplication is omitted improving speed and energy consumption at the price of a small error. The proposed approach is applicable to both signed and unsigned multiplications. We propose three hardware implementations of the Sub-Scalar Computations multiplier that includes one for the unsigned and two for the signed operations. The efficiency of the proposed multiplier is evaluated by comparing its performance with those of some Sub-Scalar Computations and accurate multipliers using different design parameters. In addition, the efficacy of the proposed Sub-Scalar Computations multiplier is studied in two image processing applications, i.e., image sharpening and smoothing.

  IJCRT's Publication Details

  Unique Identification Number - IJCRT2309312

  Paper ID - 244073

  Page Number(s) - c663-c672

  Pubished in - Volume 11 | Issue 9 | September 2023

  DOI (Digital Object Identifier) -   

  Publisher Name - IJCRT | www.ijcrt.org | ISSN : 2320-2882

  E-ISSN Number - 2320-2882

  Cite this article

  D. GEETHANJALI1,  P. YASODHA DEVI,   "DESIGN & IMPLEMENTATION OF LOW POWER & HIGH FAST SUBSCALAR MULTIPLIER", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.11, Issue 9, pp.c663-c672, September 2023, Available at :http://www.ijcrt.org/papers/IJCRT2309312.pdf

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ISSN: 2320-2882
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Journal Starting Year (ESTD) : 2013
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ISSN and 7.97 Impact Factor Details


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ISSN: 2320-2882
Impact Factor: 7.97 and ISSN APPROVED
Journal Starting Year (ESTD) : 2013
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