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INTERNATIONAL JOURNAL OF CREATIVE RESEARCH THOUGHTS - IJCRT (IJCRT.ORG)
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ISSN Approved Journal No: 2320-2882 | Impact factor: 7.97 | ESTD Year: 2013
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Paper Title
PERFORMANCE ANALYSIS OF 16BIT-MAC UNIT USING VEDIC AND BOOTH MULTIPLIER
Authors
Samanthapudi Swathi, PSSN Mowlika, R DEVI, D BHAVANI
Keywords
Vedic mathematics, carry-save adder, MAC unit, Verilog HDL, Look-up Table
Abstract
Multiply and Accumulate operation is one of the fundamental methods in signal processing and other areas (MAC). A digital signal processor's (DSP's) multiplier is the device's single most important physical component. Power consumption, LUT use, and latency are the limited factors in Digital signal processors performance. The development of a low-power, low-latency multiplier is so essential. The study's focus is on finding the best design for a 16-bit MAC unit that employs a multiplier and a carry save adder with a bit depth of 8. We may make use of the booth multiplier as a benchmark. Verilog HDL is used throughout the whole of the design's implementation. Vivado 2018.2 was used for both the synthesis and the simulation. The proposed architecture provides a means of drastically cutting down on the waiting time. The energy consumption is reduced by almost 15% as a result.
IJCRT's Publication Details
Unique Identification Number - IJCRT2303463
Paper ID - 232436
Page Number(s) - e106-e110
Pubished in - Volume 11 | Issue 3 | March 2023
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Publisher Name - IJCRT | www.ijcrt.org | ISSN : 2320-2882
E-ISSN Number - 2320-2882
Cite this article
Samanthapudi Swathi, PSSN Mowlika, R DEVI, D BHAVANI, "PERFORMANCE ANALYSIS OF 16BIT-MAC UNIT USING VEDIC AND BOOTH MULTIPLIER", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.11, Issue 3, pp.e106-e110, March 2023, Available at :http://www.ijcrt.org/papers/IJCRT2303463.pdf
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ISSN: 2320-2882 Impact Factor: 7.97 and ISSN APPROVED Journal Starting Year (ESTD) : 2013
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ISSN: 2320-2882 Impact Factor: 7.97 and ISSN APPROVED Journal Starting Year (ESTD) : 2013
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