Published Paper Details:

In this study, an unique concept to estimation circuit model is proposed, based on the creation and use of fictitious timing routes, or critical paths that cannot be logically actuated. By ensuring modest and controlled transformation, this enables a significant relaxation of temporal limitations. By using high-significance stages to break the carry propagation chain at lower numbers, the Carry Cut-Back Adder (CCBA), a rough adder design, implements this technique. By preventing the carry chain's logic from triggering, this simple method offers reduced worst-case errors while boosting performance and energy sustainability. The document contains a design methodology as well as implementation, error optimization, and design space minimization. Very reliability has been revealed to be possible with the CCBA, and it also offers tremendous circuit savings. Energy savings of up to 36% as compared to exact adders are shown with a worst-case reliability of 99.999%. The comparison of 32-bit estimate and truncated adders for mean and worst-case relative errors is then carried out in the context of industry. The CCBA beats both state-of-the-art and truncated adders for high-accuracy and low-power circuits, highlighting the potential of the suggested idea to contribute to the creation of highly efficient estimate or precision-scalable hardware accelerators.