Published Paper Details:

Traditional guided test benches are no longer a practical testing solution due to the increasing design complexity of integrated circuits. Verification is a technique that can be used to show that a design is functionally sound. Automation reduces the likelihood of human error in the process. Automation completely eliminates human involvement from the Method. Automation, however, is not always feasible, particularly in poorly defined processes that nonetheless need for human intelligence and originality, like hardware design. There is an increasing need for guidelines and best practices to ensure successful verification IPs because testing has been replaced by verification utilizing verification IPs in modern times. In order to overcome the verification challenge of complicated Ethernet IP, a full truncation level verification environment is proposed in this paper. The most popular network architecture in use today is Ethernet. The project's primary goal is to test the Ethernet IP with various interfaces. Additionally, it covers the verification method and reuse of the design environment. Multiple degrees of reuse will be possible in the verification environment suggested by System Verilog, both inside and between projects. For simulation, we are utilising Mentor graphics Questasim.