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  Published Paper Details:

  Paper Title

DESIGN METHODOLOGY OF ERROR REDUCED APPROXIMATE ADDERS FOR FPGAS

  Authors

  M.Karthiga,  Dr.S.Mohideen Abdul Kadhar

  Keywords

Approximate computing, approximate adder structure , FPGA, Low power designs, Low area designs LUT

  Abstract


In this paper, we propose novel low error approximate adder structures for FPGA-based implementations. By using the proposed adder structures, the throughput of an FPGA-based implementation can be significantly increased. We propose two approximate adder structurers for FPGAs in this paper : one is low error and area efficient approximate adder (LEADx), and another one is area and power efficient approximate adder (APEx). Both approximate adders are consists of an accurate and an approximate part. These kind of adders are designed to minimize the mean square error (MSE). When compared with other approximate adders LEADx has lower MSE whereas APEx has smaller area and lower power consumption. When compared with other existing approximate adders LEADx provided better quality for video encoding application

  IJCRT's Publication Details

  Unique Identification Number - IJCRT2208504

  Paper ID - 224876

  Page Number(s) - e146-e152

  Pubished in - Volume 10 | Issue 8 | August 2022

  DOI (Digital Object Identifier) -   

  Publisher Name - IJCRT | www.ijcrt.org | ISSN : 2320-2882

  E-ISSN Number - 2320-2882

  Cite this article

  M.Karthiga,  Dr.S.Mohideen Abdul Kadhar,   "DESIGN METHODOLOGY OF ERROR REDUCED APPROXIMATE ADDERS FOR FPGAS", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.10, Issue 8, pp.e146-e152, August 2022, Available at :http://www.ijcrt.org/papers/IJCRT2208504.pdf

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ISSN: 2320-2882
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Journal Starting Year (ESTD) : 2013
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ISSN and 7.97 Impact Factor Details


ISSN
ISSN
ISSN: 2320-2882
Impact Factor: 7.97 and ISSN APPROVED
Journal Starting Year (ESTD) : 2013
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