Published Paper Details:

The pulse-triggered flip-flop (P-FF) is proposed and proved as a novel sort of very efficient conditional feed. Pre discharging and conditional signal feed through methods were used to reduce the data-to-output (D-to-Q) delay in this circuit. A shared pulse generator and an output feedback-controlled conditional keeper were also used to cut power consumption, lowering the internal node's floating state. An additional pull-down path was added to the output node to improve the driving strength of this design. Various post-layout simulation studies using 16-nm Fin FET technology showed that the suggested topology has a greater energy efficiency (at all input data toggle rates) than comparable P-FF devices. In comparison to a transmission gate FF, the proposed model achieved a 62 percent D-to-Q delay reduction, exceeding the device by more than 66 percent in terms of power efficiency and 87 percent in terms of energy efficiency (at a 50 percent input data toggle rate). In comparison to other traditional P-FFs, the improvements were significantly more considerable. These results suggest the proposed design to be a viable new option for high-efficiency sequential elements in high-speed applications.