Published Paper Details:

As a result of the growing number of computer and signal processing applications, there has been an increase in demand for high-speed processing. In multiplier design, low power consumption is also a major consideration. A good multiplier should be able to provide a physically compact, high-speed device with low power consumption. The multipliers used in digital systems decide the power consumption and speed of such systems. In order to increase the efficiency of any processor, it must utilize an efficient multiplication algorithm. The main objective here is to present a model of a n*n bit optimized multiplier architecture with low power and high speed using different algorithms and optimized full adders with low power dissipation and minimum propagation delay. The algorithms in this proposed architecture multiplier are Vedic multiplier, Wallace, and Dadda. The algorithms work by reducing the number of steps in the process that include partial products. The partial products are added to get the algorithm's output. The number of partial products determines the speed