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  Published Paper Details:

  Paper Title

IMPLEMENTATION OF SEQUENCE DETECTOR USING REVERSIBLE LOGIC

  Authors

  N Srinivasa Rao

  Keywords

Finite state machine, Sequence detector, Verilog HDL, Xilinx, Reversible logic

  Abstract


For any complex digital systems, design and analysis through state machine approach is preferred. In this paper, sequence detector using Mealy finite state machine is designed with reversible logic circuits. Reducing power dissipation is the main requirement for low power VLSI design. Reversible logic circuits have received more attention in the recent years because of their ability to reduce the power dissipation. The behavior of these circuits are described in Verilog HDL, Simulated and Synthesized in Xilinx ISE environment. In this work, sequence detectors with and without overlap sequence are considered

  IJCRT's Publication Details

  Unique Identification Number - IJCRT2102616

  Paper ID - 203920

  Page Number(s) - 5112-5117

  Pubished in - Volume 9 | Issue 2 | February 2021

  DOI (Digital Object Identifier) -    http://doi.one/10.1729/Journal.25983

  Publisher Name - IJCRT | www.ijcrt.org | ISSN : 2320-2882

  E-ISSN Number - 2320-2882

  Cite this article

  N Srinivasa Rao,   "IMPLEMENTATION OF SEQUENCE DETECTOR USING REVERSIBLE LOGIC", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.9, Issue 2, pp.5112-5117, February 2021, Available at :http://www.ijcrt.org/papers/IJCRT2102616.pdf

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ISSN: 2320-2882
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Journal Starting Year (ESTD) : 2013
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ISSN and 7.97 Impact Factor Details


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ISSN
ISSN: 2320-2882
Impact Factor: 7.97 and ISSN APPROVED
Journal Starting Year (ESTD) : 2013
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