Published Paper Details:

Data comparators are key arithmetic units used in digital systems to know whether two numbers are equal, or one number is less than or greater than other number. In this work a novel Area and power efficient multiplexer based Data comparator is proposed. The proposed method uses multiplexer to implement borrow equation in a full subtractor .which acts as a elementary processing element of a Data Comparator. The proposed designs are implemented in Dsch tool for gate level designs of AND gate ,OR gate, Multiplexer, Barrow generation unit and high and low value output units and verilog file is generated . Microwind tool is used to get layouts for different Models of Mosfet and different technologies. The moderations in the existing borrow equation of a full subtractor using multiplexer only resulted in reduced number of transistors with lower power. It was found that a 8 bit data comparator will require only 110 transistors and dissipates 17.25uw of power for 90nm technology