Published Paper Details:

The increasing complexity of the Very Large Scale Integration (VLSI) circuits necessitates miniaturization and fabrication of the nano-scale device in the intricate manufacturing process. However, this had led to greater process variation, higher probability of defects and worsened the manufacturing yield. Various Automatic Test Pattern Generation (ATPG) tools available today employ powerful heuristics and are capable of generating efficient and compact test sets for a Circuit-Under-Test (CUT). These tools provide tests with high fault coverage, and identify redundant faults in the CUT to a large extent, even though the underlying problem is known to be computationally hard. But, the production tests are primarily aimed only for fault detection and they may not be very efficient for diagnosis. Linear Feedback Shift Registers (LFSRs) are the most widely used pseudorandom Test Pattern Generators (TPGs) in Built-In Self-Test (BIST) systems. This proposes a combined testing methodology for the scan-based BIST. A smoother and Geffe generator are included in the TPG to reduce average power consumption during scan testing, while a group-based selection algorithm is employed for the scan-chain reorder in order to improve the fault coverage. The objective is to produce test pattern with good randomness; then the fault coverage will be better. Fault simulation is done using Xilinx. From the experimental results, it is observed that the proposed methodology achieves better performance than the existing methods.