Published Paper Details:

Deep learning such as Convolutional Neural Networks (CNNs) are an important workload increasingly demanding high-performance hardware acceleration. One distinguishing feature of deep learning workload is that it is inherently resilient to small numerical errors and works very well with low precision hardware. This paper presents a novel method to double the computation rate of convolutional neural network (CNN) accelerators by packing two multiply-and-accumulate (MAC) operations into one DSP block of off-the-shelf FPGAs (called Double MAC).There are several technical challenges, which we overcome by exploiting the mode of operation in the CNN accelerator. We have validated our method through FPGA synthesis and Verilog simulation, and evaluated our method by applying it to the state-of-the art CNN accelerator. While a general SIMD MAC using a single DSP block seems impossible, our solution is tailored for the kind of MAC operations required for a convolution layer. We find that our Double MAC approach can increase the computation throughput of a CNN layer by twice. In this paper we implement a Multiply Accumulate (MAC) unit based on a modified 8-bit Ripple carry adder which is again replaced by 8-bit Kogge Stone adder (KSA) for a DSP module in order to achieve high throughput. Our evaluation results shows that not only our Double MAC approach can increase the computation throughput of a CNN layer by twice with essentially reduced area, delay and power