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  Published Paper Details:

  Paper Title

VLSI ARCHITECTURE OF RECONFIGURABLE HARD DECISION VITERBI DECODER

  Authors

  N.Glory Priscilla,  D.Vijayasri,  Dr.M.Ramesh Patnaik

  Keywords

Error correcting code, convolutional codes, Viterbi algorithm, convolutional codes.

  Abstract


In order to control errors in data transmission through a noisy channel Viterbi algorithm has served as a powerful tool meant for interpreting the conventional codes. It is centred on extreme possibility algorithm for interpreting the data? While coming to hardware implementation of Viterbi algorithm became crucial as it drain large amount of assets because of its complexity. This paper confers the implementation of an efficient VHDL execution of a Viterbi decoder by means of the concept of pipelining to diminish the critical path. There by improving the operating frequency of the design and improving the through put using Modalism and Xilinx ISE tools for simulation and synthesis of modules respectively.

  IJCRT's Publication Details

  Unique Identification Number - IJCRT2007383

  Paper ID - 197124

  Page Number(s) - 3725-3731

  Pubished in - Volume 8 | Issue 7 | July 2020

  DOI (Digital Object Identifier) -   

  Publisher Name - IJCRT | www.ijcrt.org | ISSN : 2320-2882

  E-ISSN Number - 2320-2882

  Cite this article

  N.Glory Priscilla,  D.Vijayasri,  Dr.M.Ramesh Patnaik,   "VLSI ARCHITECTURE OF RECONFIGURABLE HARD DECISION VITERBI DECODER", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.8, Issue 7, pp.3725-3731, July 2020, Available at :http://www.ijcrt.org/papers/IJCRT2007383.pdf

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ISSN: 2320-2882
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Journal Starting Year (ESTD) : 2013
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ISSN and 7.97 Impact Factor Details


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ISSN
ISSN: 2320-2882
Impact Factor: 7.97 and ISSN APPROVED
Journal Starting Year (ESTD) : 2013
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