Published Paper Details:

Processing of a digital image by the use of computer algorithm is usually referred as digital image processing. Image filtering is one of the very useful techniques in image processing and computer vision. It is used to remove some unwanted signals capture the image and termed as noise . Digital filters are an integral part of signal processing which help us to remove the frequencies which are of less importance or considered unwanted, also termed as noise sometimes. Thus the digital image filtering technique is frequently used to eliminate noise. Generally image filters follows software approach in systems. But hardware implementation prefered in comparison with software implementation for better processing speed. With a boost in the VLSI technology hardware implementation has given a better choice. This project presents the design of a new hardware accelerator, filtering the input data using Gabor and Box functions and dedicated to image processing. The proposed design obtains a great reduction in terms of resources compared to other state-of-the-art implementations. In this work, a comparative study on FPGA implementation of both the Gabor filter and Box filter is presented. Simulation and Synthesis is done using Xilinx ISE design suite. Verilog code will be used as a description language for mapping algorithm in VLSI and hardware implementation on SPARTAN-3 FPGA.