Published Paper Details:

The digital world we live in demands a high application of digital signal processing, neural networking, computer automation. Multiplier is one of the essential operators for these applications. The demand for power efficiency and higher speed introduces errors into these applications. These demands give birth to a new field known as Approximate computing. In the paper approximate multiplier is designed with a huge range of dynamic selection. One of the main advantages of the design is the error introduced during a computation, which cancels with previous computation instead of summing up. An approximate DRUM multiplier is designed using Verilog. Register Transfer Level (RTL) is retrieved. The computation of error metrics is done in MATLAB. This design is scalable and so it can be used according to the required application. The propagation delay of the multiplier is reduced in this design which makes it faster. Error analysis is done based on various parameters and it is observed the error introduced is least among all the approximate multipliers. Since multiplier consumes more power in the processor, this multiplier is designed with power efficiency as one of the major constrain. As designed the multiplier when used in a processor saves power to 58 %. The design outperforms various other approximate multipliers which was analyzed during the literature survey. After analyzing the DRUM multiplier a modification is done in the design to improve the accuracy. This optimized design is termed as Optimized DRUM multiplier and it is analyzed and the comparative study between both the multipliers is made in terms of accuracy.