Published Paper Details:

To increase the interconnect resistance, length, and inter-wire capacitance we are going with deep sub micrometer CMOS process technology which contribute to large on-chip propagation delay. Data transmitted over interconnect determine the propagation delay and delay is extremely significant when adjacent wires are transitioning in opposite directions (i.e; crosstalk transitions) as compared to transitioning within the same direction. As a result, the degradation of high-speed digital circuits thanks to crosstalk. Crosstalk may be a phenomenon by which a logic transmitted in vlsi circuit or net/wire creates undesired effect on the neighbouring circuit or nets/wires, thanks to capacitive coupling. Reduction of crosstalk has become more important for the high-speed digital circuits. We are reducing the crosstalk by exploiting Fibonacci number system. We propose a family of Fibonacci coding techniques for crosstalk avoidance, relate them to a number of the prevailing crosstalk avoidance techniques by using the CADENCE TOOLS and simulate the codes for the reduction of crosstalk..