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  Published Paper Details:

  Paper Title

A MODIFIED RADIX-4 ARCHITECTURE TO IMPROVE THE SPEED OF DIGITAL SIGNAL PROCESSOR USING VLSI IMPLEMENTATION

  Authors

  S.Gokul,  V.Kishorekumar,  M.Bennish

  Keywords

FFT, SDC, DFT, DIT, DIF

  Abstract


This paper presents a modified Radix - 4 architecture to compute Discrete Fourier Transform (DFT) using FFT architecture to reduce the computation time and power thereby increase the speed of the Digital Signal processor. The proposed design reduces the number of multipliers and adders that are used to compute large sequence of real time data signals with less power consumption. This is achieved by avoiding repeated multiplication of twiddle factor (real and complex values) which makes the delay in the computation of FFT. The twiddle factor value is already calculated with the number of input bits to be used and the value is stored in the register. The value is called whenever the FFT requires twiddle factor for computation. The appropriate twiddle factor is selected using 3 x 8 decoder. The modified Radix-4 FFT architecture is designed, implemented and simulated using the software Xilinx - Spartan 3E version 8.2.

  IJCRT's Publication Details

  Unique Identification Number - IJCRT1872366

  Paper ID - 184129

  Page Number(s) - 1278-1283

  Pubished in - Volume 6 | Issue 1 | March 2018

  DOI (Digital Object Identifier) -    http://doi.one/10.1729/IJCRT.17412

  Publisher Name - IJCRT | www.ijcrt.org | ISSN : 2320-2882

  E-ISSN Number - 2320-2882

  Cite this article

  S.Gokul,  V.Kishorekumar,  M.Bennish,   "A MODIFIED RADIX-4 ARCHITECTURE TO IMPROVE THE SPEED OF DIGITAL SIGNAL PROCESSOR USING VLSI IMPLEMENTATION", International Journal of Creative Research Thoughts (IJCRT), ISSN:2320-2882, Volume.6, Issue 1, pp.1278-1283, March 2018, Available at :http://www.ijcrt.org/papers/IJCRT1872366.pdf

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ISSN: 2320-2882
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ISSN and 7.97 Impact Factor Details


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ISSN: 2320-2882
Impact Factor: 7.97 and ISSN APPROVED
Journal Starting Year (ESTD) : 2013
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